Avago Technologies LSI53C1000R User Manual
Page 137
SCSI Registers
4-25
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
the arbitration sequence is complete. If a sequence is
aborted, check bit 4 in the SCNTL1 register to verify that
the LSI53C1000R is not connected to the SCSI bus.
WATN
Select with SATN/ on a Start Sequence
4
When this bit is set and the LSI53C1000R is in the initiator
mode, the SATN/ signal is asserted during selection of a
SCSI target device. This is to inform the target that the
LSI53C1000R has a message to send. If a selection
time-out occurs while attempting to select a target device,
SATN/ is deasserted at the same time SSEL/ is
deasserted. When this bit is cleared, the SATN/ signal is
not asserted during selection. When executing SCSI
SCRIPTS, this bit is controlled by the SCRIPTS processor,
but manual setting is possible in the low level mode.
EPC
Enable Parity/CRC/AIP Checking
3
When this bit is set and the SCSI transfers are
asynchronous or ST synchronous, the SCSI data bus is
checked for odd parity when data is received from the SCSI
bus in either the initiator or the target mode. If a parity error
is detected, bit 0 of the
SCSI Interrupt Status Zero (SIST0)
register is set and an interrupt may be generated.
When SCSI transfers are DT synchronous, the CRC is
checked when the target requests a CRC transfer using
the DP0 signal on the SCSI bus. If a CRC error is
detected, bit 0 of the
SCSI Interrupt Status Zero (SIST0)
register is set and an interrupt may be generated.
If the LSI53C1000R SCSI function is operating in the
initiator mode and a parity error or CRC error is detected,
SATN/ can optionally be asserted, but the transfer
continues until the target changes phase or the block
move in which the parity error was detected completes.
When this bit is clear, parity errors are not reported. CRC
errors are reported in bit 0 of the
SCSI Interrupt Status Zero (SIST0)
. To disable CRC
checking and reporting, set bit 7, Disable CRC Checking,
of
.
CRCOK
CRC Request OK
2
This bit indicates it is acceptable to force a CRC request.
This bit is set only if a CRC request has been sent and
no data has been transferred since the request. This bit