Avago Technologies LSI53C1000R - Manual (Page 233)

SCSI Registers 4-121
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0xE2
CRC Control Zero (CRCCNTL0)
Read/Write
DCRCC Disable CRC Checking 7
Setting this bit causes the internal logic not to check or
report CRC errors during Ultra160 transfers. The
LSI53C1000R continues to calculate and send CRCs as
requested by the target according to the SPI-3
specification.
DCRCPC Disable CRC Protocol Checking 6
Setting this bit causes the internal logic to neither check
nor report CRC protocol errors during Ultra160 transfers.
The LSI53C1000R continues to calculate and send
CRCs as requested by the target according to the SPI-3
specification, but does not set an SGE interrupt if a CRC
protocol error occurs. This bit should not be set in normal
operations.
R Reserved [5:0]
Register: 0xE3
CRC Control One (CRCCNTL1)
Read/Write
CRCERR CRC Error 7
This bit indicates whether or not a CRC error has been
detected during a DT Data-In SCSI transfer. This bit is set
independent of the DCRCC bit. To clear this condition,
either write this bit to a 1 or read the SIST0 and SIST1
registers. When CRC Checking and the Parity/CRC/AIP
Error Interrupt are enabled, this error condition is also
indicated as a Parity/CRC/AIP error (bit 0 of the
SIST0 register).
7 6 5 0
DCRCC DCRCPC R
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
CRCERR R ENAS TSTSD TSTCHK TSTADD CRCDSEL
0 0 0 0 0 0 0 0