Max_lat (ml), Min_gnt (mg), Register: 0x3e – Avago Technologies LSI53C1000R User Manual
Page 129: Register: 0x3f
PCI Configuration Registers
4-17
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x3E
Min_Gnt (MG)
Read Only
MG
Min_Gnt
[7:0]
This register specifies the desired settings for latency
timer values. Min_Gnt specifies how long a burst period
the device needs. The value specified in these registers
is in units of 0.25
µ
s. The LSI53C1000R sets this register
to 0x11.
Register: 0x3F
Max_Lat (ML)
Read Only
ML
Max_Lat
[7:0]
This register specifies the desired settings for latency
timer values. Max_Lat specifies how often the device
needs to gain access to the PCI bus. The value specified
in this register is in units of 0.25
µ
s. The LSI53C1000R
sets this register to 0x12, indicating it needs the bus
every 4.5
µ
s to maintain a data stream of 160 Mbytes/s.
7
0
MG
0
0
0
1
0
0
0
1
7
0
ML
0
0
0
1
0
0
1
0