Table 4.5 single transition transfer rates, Single transition transfer rates, Table 4.5 – Avago Technologies LSI53C1000R User Manual
Page 222
4-110
Registers
Version 2.2
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40
4
4
100.00
5.00
2.50
40
8
0
200.00
2.50
2.50
40
8
1
200.00
2.50
2.00
40
8
2
200.00
2.50
1.67
40
8
3
200.00
2.50
1.43
40
8
4
200.00
2.50
1.25
1. Number Xclks = XCLKS_DT + XCLKS_ST + XCLKH_DT + XCLKH_ST.
Table 4.5
Single Transition Transfer Rates
Clock
(MHz)
Divisor
Number
Xclks
1
Base
Period
(ns)
Receive Rate
(Megatransfers/)
Send Rate
(Megatransfers/s)
160
1
0
6.25
40.00
40.00
160
1
1
6.25
40.00
32.00
160
1
2
6.25
40.00
26.67
160
1.5
0
9.38
26.67
26.67
160
1.5
1
9.38
26.67
21.33
160
1.5
2
9.38
26.67
17.78
160
2
0
12.50
20.00
20.00
160
2
1
12.50
20.00
16.00
160
2
2
12.50
20.00
13.33
160
3
0
18.75
13.33
13.33
Table 4.4
DT Transfer Rates (Cont.)
Clock
(MHz)
Divisor
Number
Xclks
1
Base
Period
(ns)
Receive Rate
(Megatransfers/)
Send Rate
(Megatransfers/)
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