Avago Technologies LSI53C1000R - Manual (Page 61)

SCSI Functional Description 2-31
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.2.5.5 Using the SCSI Clock Quadrupler
The LSI53C1000R can quadruple the frequency of a 40 MHz SCSI clock,
allowing the system to perform Ultra160 SCSI transfers. This option is
user-selectable with bit settings in the
SCSI Test One (STEST1) ,
SCSI Test Three (STEST3) , and SCSI Control Three (SCNTL3)
registers. At power-on or reset, the quadrupler is disabled and powered
down. Follow these steps to use the clock quadrupler:
1. Set the SCLK Quadrupler Enable bit ( SCSI Test One (STEST1)
register, bit 3).
2. Do not poll bit 5 of the SCSI Test Four (STEST4) register. Bit 5 is
reserved. Use a delay of 50
µ
s after the quadrupler enable bit is set
in step 1.
3. Halt the SCSI clock by setting the Halt SCSI Clock bit
(
SCSI Test Three (STEST3) register, bit 5).
4. Set the clock conversion factor using the SCF (Synchronous clock
Conversion Factor) field in the
SCSI Control Three (SCNTL3) register.
5. Set the SCLK Quadrupler Select bit ( SCSI Test One (STEST1) , bit 2).
6. Clear the Halt SCSI Clock bit.
2.2.6 Prefetching SCRIPTS Instructions
The prefetch logic in the LSI53C1000R fetches 8 Dwords of instructions
when enabled by setting the Prefetch Enable bit (bit 5) in the
DMA Control (DCNTL) register. The maximum burst size that can be
performed is automatically determined using the burst length values in
the
DMA Mode (DMODE) register. If the unit cannot perform bursts of at
least 4 Dwords, it disables itself. While the chip is prefetching SCRIPTS
instructions, it uses the PCI cache commands Memory Read Line and
Memory Read Multiple, if PCI caching is enabled.
Note: This feature is only useful when fetching SCRIPTS
instructions from main memory. Due to the short access
time of SCRIPTS RAM, prefetching is not necessary when
fetching instructions from SCRIPTS RAM.