Avago Technologies LSI53C1000R User Manual
Page 200
4-88
Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
R
Reserved
6
HSC
Halt SCSI Clock
5
Asserting this bit causes the internal divided SCSI clock
to come to a stop in a glitchless manner. This bit is used
for test purposes or to lower I
DD
during a power-down
mode. Refer to
Chapter 2, “Functional Description,”
for
operation of the SCSI clock quadrupler.
DSI
Disable Single Initiator Response
4
If this bit is set, the LSI53C1000R ignores all bus-initiated
selection attempts that employ the single-initiator option
from SCSI-1. In order to select the LSI53C1000R while
this bit is set, the LSI53C1000R’s SCSI ID and the
initiator’s SCSI ID must both be asserted. Assert this bit
in SCSI-2 systems so that a single bit error on the SCSI
bus is not interpreted as a single initiator response.
R
Reserved
3
TTM
Timer Test Mode
2
Asserting this bit facilitates testing of the selection
time
−
out, general purpose, and handshake-to-handshake
timers by greatly reducing all three time-out periods.
Setting this bit starts all three timers. If the respective bits
in the
SCSI Interrupt Enable One (SIEN1)
register are
asserted, the LSI53C1000R generates interrupts at
time-out. This bit is intended for internal manufacturing
diagnosis and should not be used in normal operation.
CSF
Clear SCSI FIFO
1
Setting this bit causes the “full flags” for the SCSI FIFO to
be cleared. This empties the FIFO. This bit is self-clearing.
In addition to the SCSI FIFO pointers, the SIDL, SODL,
and SODR full bits in the
and
are cleared.
R
Reserved
0