Avago Technologies LSI53C1000R - Manual (Page 317)

PCI and External Memory Interface Timing Diagrams 6-35
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.22 Burst Read, 64-Bit Address and Data
t
1
t
2
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by LSI53C1000R)
GPIO1_MASTER/
(Driven by LSI53C1000R)
REQ/
(Driven by LSI53C1000R)
PAR; PAR64
(Addr drvn by LSI53C1000R;-
IRDY/
(Driven by LSI53C1000R)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
AD[31:0]
(Driven by LSI53C1000R-
C_BE[3:0]/
(Driven by LSI53C1000R)
t
3
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C1000R)
Addr
Out Lo
t
2
Addr; Target-Data)
Data drvn by Target)
BE
Data In
Out In In
REQ64/
(Driven by LSI53C1000R)
ACK64/
(Driven by Target)
Addr
Out Hi
t
2
Bus Dual
Addr CMD
AD[63:32]
(Driven by LSI53C1000R-
C_BE[7:4]/
(Driven by LSI53C1000R)
Addr; Target-Data)
BE
Data In
Hi Address
Bus CMD
In