Avago Technologies LSI53C1000R - Manual (Page 103)

PCI Bus Interface Signals 3-9
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
3.3.5 Error Reporting Signals
Table 3.6 describes the Error Reporting Signals group.
3.3.6 Interrupt Signals
Table 3.7 describes the Interrupt Signals group.
Table 3.6 Error Reporting Signals
Name Bump Type Strength Description
PERR/ AE17 S/T/S 8 mA PCI Parity Error may be pulsed active by an agent that detects
a data parity error. PERR/ can be used by any agent to
signal data corruption. On detection of a PERR/ pulse, the
central resource may generate a nonmaskable interrupt to
the host CPU, which often implies the system is unable to
continue operation once error processing is complete.
SERR/ AC17 O 8 mA PCI System Error is an open drain output that reports address
parity errors as well as critical errors other than parity.
Table 3.7 Interrupt Signals
Name Bump Type Strength Description
INTA/ AC8 O 8 mA PCI Interrupt. This signal, when asserted LOW, indicates that
an interrupt condition requires service from the host CPU.
The output drive of this pin is an open drain. Refer to
SCSI Test One (STEST1) , bits [1:0], for additional
information about disabling this interrupt in a RAID
environment. This interrupt pin is disabled if INT_DIR is
driven LOW.
ALT_INTA/ AF7 O 8 mA PCI Alt Interrupt. This signal, when asserted LOW, indicates
that an interrupt condition requires service from the host
CPU. The output drive of this pin is an open drain. Refer to
SCSI Test One (STEST1) , bits [1:0], for additional
information about disabling this interrupt in a RAID
environment. This interrupt pin is disabled if INT_DIR is
driven LOW.