Avago Technologies LSI53C1000R - Manual (Page 108)

3-14 Signal Descriptions
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
3.6 Flash ROM and Memory Interface Signals
Table 3.12 describes the Flash ROM and Memory Interface Signal groups.
Table 3.12 Flash ROM and Memory Interface Signals
Name Bump Type Strength Description
MWE/ H23 O 4 mA Memory Write Enable. This pin is a write enable
signal to an external flash memory.
MCE/ G25 O 4 mA Memory Chip Enable. This pin is a chip enable
signal to an external EEPROM or flash memory
device.
MOE/ G26 O 4 mA Memory Output Enable. This pin is an output
enable signal to an external EEPROM or flash
memory during read operations. It also tests the
connectivity of the LSI53C1000R signals in the
“AND-tree” test mode.
MAS0/ K22 O 4 mA Memory Address Strobe 0. This pin latches in the
least significant address byte (bits [7:0]) of an
external EEPROM or flash memory. Because the
LSI53C1000R moves addresses eight bits at a time,
this pin connects to the clock of an external bank of
flip-flops that assemble up to a 20-bit address for
the external memory.
MAS1/ J24 O 4 mA Memory Address Strobe 1. This pin latches in the
most significant address byte (bits [15:8]) of an
external EEPROM or flash memory. Because the
LSI53C1000R moves addresses eight bits at a time,
this pin connects to the clock of an external bank of
flip-flops that assemble up to a 20-bit address for
the external memory.
MAD[7:0] D26, E25,
H22, F24,
G23, D25,
F23, G22 I/O 4 mA Memory Address/Data Bus. This bus, in
conjunction with the memory address strobe pins
and external address latches, assembles up to a
20-bit address for an external EEPROM or flash
memory. This bus first issues the least significant
byte and finishes with the most significant bits. It
also writes data to a flash memory or read data into
the chip from external EEPROM/flash memory.
These pins have static pull-downs.