Dma status (dstat), Register: 0x0c – Avago Technologies LSI53C1000R User Manual
Page 151
SCSI Registers
4-39
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
REQ
Assert SCSI REQ/ Signal
7
ACK
Assert SCSI ACK/ Signal
6
BSY
Assert SCSI BSY/ Signal
5
SEL
Assert SCSI SEL/ Signal
4
ATN
Assert SCSI ATN/ Signal
3
MSG
Assert SCSI MSG/ Signal
2
C_D
Assert SCSI C_D/ Signal
1
I_O
Assert SCSI I_O/ Signal
0
Register: 0x0C
DMA Status (DSTAT)
Read Only
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register in case additional
interrupts are pending (the LSI53C1000R stacks interrupts). The DIP bit
in the
Interrupt Status Zero (ISTAT0)
register is also cleared. It is possible
to mask DMA interrupt conditions individually through the
register.
When performing consecutive 8-bit reads of the
SCSI Interrupt Status Zero (SIST0)
, and
SCSI Interrupt Status One (SIST1)
registers (in any order), insert a delay equivalent to 12 clock periods
between the reads to ensure that the interrupts clear properly. Refer to
Chapter 2, “Functional Description,”
for more information on interrupts.
DFE
DMA FIFO Empty
7
This status bit is set when the DMA FIFO is empty. It is
possible to use it to determine if any data resides in the
FIFO when an error occurs and an interrupt is generated.
This bit is a pure status bit and does not cause an
interrupt.
7
6
5
4
3
2
1
0
DFE
MDPE
BF
ABRT
SSI
SIR
R
IID
1
0
0
0
0
0
x
0