Avago Technologies LSI53C1000R - Manual (Page 197)

SCSI Registers 4-85
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x4D
SCSI Test One (STEST1)
Read/Write
R Reserved [7:6]
DOSGE Disable Outbound SCSI Gross Errors 5
When set, this bit disables all SCSI gross errors related
to outbound data transfers.
DISGE Disable Inbound SCSI Gross Errors 4
When set, this bit disables all SCSI gross errors related
to inbound data transfers.
QEN SCLK Quadrupler Enable 3
This bit, when set, powers up the internal clock
quadrupler circuit, which quadruples the SCLK 40 MHz
clock to the internal 160 MHz SCSI clock required for
Ultra2 and Ultra160 SCSI operation. When cleared, this
bit powers down the internal quadrupler circuit. Refer to
Chapter 2, “Functional Description,” for information
concerning the operation of the quadrupler.
QSEL SCLK Quadrupler Select 2
This bit, when set, selects the output of the internal clock
quadrupler as the internal SCSI clock. When cleared, this
bit selects the clock presented on SCLK as the internal
SCSI clock. Refer to
Chapter 2, “Functional Description,”
for information concerning the operation of the
quadrupler.
IRM[1:0] Interrupt Routing Mode [1:0]
The LSI53C1000R supports four different interrupt
routing modes. These modes are described in the
following table. Mode 0, the default mode, is compatible
with RAID upgrade products.
7 6 5 4 3 2 1 0
R DOSGE DISGE QEN QSEL IRM[1:0]
0 0 0 0 0 0 0 0