Avago Technologies LSI53C1000R - Manual (Page 332)

6-50 Specifications
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Table 6.34 Normal/Fast Memory (
≥
128 Kbytes) Single Byte Access Write Cycle
Symbol Parameter Min Max Unit
t
11
Address setup to MAS/ HIGH 25 – ns
t
12
Address hold from MAS/ HIGH 15 – ns
t
13
MAS/ pulse width 25 – ns
t
20
Data setup to MWE/ LOW 30 – ns
t
21
Data hold from MWE/ HIGH 20 – ns
t
22
MWE/ pulse width 100 – ns
t
23
Address setup to MWE/ LOW 60 – ns
t
24
MCE/ LOW to MWE/ HIGH 120 – ns
t
25
MCE/ LOW to MWE/ LOW 25 – ns
t
26
MWE/ HIGH to MCE/ HIGH 25 – ns