Avago Technologies LSI53C1000R - Manual (Page 120)

4-8 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x0D
Latency Timer (LT)
Read/Write
LT Latency Timer [7:0]
The Latency Timer register specifies, in units of PCI bus
clocks, the value of the Latency Timer for this PCI bus
master. The LSI53C1000R supports this timer. All eight
bits are writable, allowing latency values of 0–255 PCI
clocks. Use the following equation to calculate an
optimum latency value for the SCSI function.
Latency = 2 + (Burst Size * (typical wait states + 1))
Values greater than optimum are also acceptable.
Register: 0x0E
Header Type (HT)
Read Only
HT Header Type [7:0]
This 8-bit register identifies the layout of bytes 0x10
through 0x3F in configuration space and also whether or
not the device contains multiple functions. Because the
LSI53C1000R is not a multifunction controller, the value
of this register is 0x00.
7 0
LT
0 0 0 0 0 0 0 0
7 0
HT
0 0 0 0 0 0 0 0