Avago Technologies LSI53C1000R - Manual (Page 301)

PCI and External Memory Interface Timing Diagrams 6-19
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Table 6.20 Operating Register/SCRIPTS RAM Read, 64 Bits
Symbol Parameter
66 MHz PCI 33 MHz PCI
Unit Min Max Min Max
t
1
Shared signal input setup time 3 – 7 – ns
t
2
Shared signal input hold time 0 – 0 – ns
t
3
CLK to shared signal output valid 2 6 2 11 ns