Avago Technologies LSI53C1000R User Manual
Page 186
4-74
Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
SEL
Selected
5
This bit is set when the LSI53C1000R is selected by
another SCSI device. For the LSI53C1000R to respond
to selection attempts, the Enable Response to Selection
bit must be set in the
register. The
and
registers must hold the
chip’s ID.
RSL
Reselected
4
This bit is set when the LSI53C1000R is reselected by
another SCSI device. The Enable Response to
Reselection bit must be set in the
register (and the
and
registers must hold the
chip’s ID) for the LSI53C1000R to respond to reselection
attempts.
SGE
SCSI Gross Error
3
This bit is set when the LSI53C1000R encounters a
SCSI Gross Error condition. The following conditions can
result in a SCSI Gross Error:
•
Offset Underflow occurs in target mode when a
SACK/ signal is received before the corresponding
SREQ/ signal has been sent.
•
Offset Overflow occurs in initiator mode when an
SREQ/ signal is received and causes the maximum
offset, as defined by the MO[5:0] bits in the
SXFER register, to be exceeded.
•
In initiator mode, a phase change occurs with an
outstanding SREQ/SACK offset.
•
Residual Data in SCSI FIFO occurs when a transfer
other than Synchronous Data Received is started with
data left in the SCSI Synchronous Receive FIFO.
•
Multiple CRC Requests occur when, during a
synchronous DT transfer, multiple CRC requests are
received within the same offset.
•
A request for a Pad CRC word is received without the
subsequent CRC word requests.
•
A phase change occurs without a CRC Request.