Avago Technologies LSI53C1000R - Manual (Page 133)

SCSI Registers 4-21
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x47
Data
Read Only
DATA Data [7:0]
This register provides an optional mechanism for the
function to report state-dependent operating data. The
LSI53C1000R always returns 0x00.
4.2 SCSI Registers
The control registers for the SCSI core are directly accessible from the
PCI bus using Memory or I/O mapping. The address map of the SCSI
registers is shown in
Table 4.2 .
The eight, 32-bit, phase mismatch registers contain the byte count and
addressing information required to update the Direct, Indirect, or
Table Indirect BMOV instructions with new byte counts and addresses. The
phase mismatch registers are the
Phase Mismatch Jump Address One (PMJAD1) ,
Phase Mismatch Jump Address Two (PMJAD2) ,
Remaining Byte Count (RBC) , Updated Address (UA) ,
Entry Storage Address (ESA) , Instruction Address (IA) ,
SCSI Byte Count (SBC) , and the Cumulative SCSI Byte Count (CSBC) .
All the phase mismatch registers can be read/written using the
Load and Store SCRIPTS instructions, Memory-to-Memory Moves,
Read/Write SCRIPTS instructions, or the CPU with SCRIPTS not running.
Note: The only registers that the host CPU can access while the
LSI53C1000R is executing SCRIPTS are the
Interrupt Status Zero (ISTAT0) , Interrupt Status One (ISTAT1) ,
Mailbox Zero (MBOX0) , and Mailbox One (MBOX1) registers;
attempts to access other registers interfere with the operation
of the chip. However, all operating registers are accessible
with SCRIPTS. All read data is synchronized and stable
when presented to the PCI bus.
Note: Do not access reserved bits or registers.
7 0
DATA
0 0 0 0 0 0 0 0