Avago Technologies LSI53C1000R - Manual (Page 79)

SCSI Functional Description 2-49
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Some SCSI interrupts are nonfatal. The SCSI interrupts are indicated by
the SIP bit in the
Interrupt Status Zero (ISTAT0) register and one or more
bits in SCSI Interrupt Status Zero (SIST0) register or
SCSI Interrupt Status One (SIST1) register.
When the LSI53C1000R is operating in the Initiator mode,
Interrupt-on-the-Fly, Function Complete (CMP), Selected (SEL),
Reselected (RSL), General Purpose Timer Expired (GEN), and
Handshake-to-Handshake Timer Expired (HTH) interrupts are nonfatal.
When operating in the Target mode, Interrupt-on-the-Fly, SATN/ active
(M/A), CMP, SEL, RSL, GEN, and HTH are nonfatal. Refer to the
description for the Disable Halt on a Parity/CRC/AIP Error or SATN/
active (Target Mode Only) bit, DHP, in the
SCSI Control One (SCNTL1)
register to configure the chip’s behavior when the SATN/ interrupt is
enabled during Target mode operation.
The reason for nonfatal interrupts is to prevent the SCRIPTS from stopping
when an interrupt occurs that does not require service from the CPU. This
prevents an interrupt when arbitration is complete (CMP set), when the
LSI53C1000R is selected or reselected (SEL or RSL set), when the initiator
asserts ATN (target mode: SATN/ active), or when the General Purpose or
Handshake-to-Handshake timers expire. These interrupts are not needed
for events that occur during high level SCRIPTS operation.
2.2.16.4 Masking
Masking an interrupt means disabling or ignoring that interrupt. Clearing
bits in the
SCSI Interrupt Enable Zero (SIEN0) and
SCSI Interrupt Enable One (SIEN1) registers masks SCSI interrupts.
Clearing bits in the DMA Interrupt Enable (DIEN) register masks DMA
interrupts. Masking an interrupt after INTA/ is asserted does not cause
INTA/ to be negated. How the chip responds to masked interrupts
depends on whether polling or hardware interrupts are being used;
whether the interrupt is fatal or nonfatal; and whether the chip is
operating in the Initiator or Target mode.
If a nonfatal interrupt occurs while masked, SCRIPTS continues. The
appropriate bit in the
SCSI Interrupt Status Zero (SIST0)
or SCSI Interrupt Status One (SIST1) is still set, the SIP bit in the
Interrupt Status Zero (ISTAT0) is not set, and the INTA/ pin is not asserted.