Avago Technologies LSI53C1000R - Manual (Page 381)

Index IX-9
read multiple 2-12 , 2-13
read multiple command 2-7
space 2-3 , 2-4
to memory 2-18
to memory moves 2-18
write 2-12 , 2-13
write and invalidate 2-12
write and invalidate command 2-9
write caching 2-13
write command 2-6
write enable 3-14
Min_Gnt (MG[7:0]) 4-17
MOE/ 3-14
move to/from SFBR cycles 5-25
multiple cache line transfers 2-10
MWE/ 3-14
N
new capabilities (NC) 4-6
next_item_ptr (NIP[7:0]) 4-18
no flush 5-35
store instruction only 5-39
nonburst opcode fetch 32-bit address and data 6-24
none 2-61
nonfatal interrupts 2-48
normal/fast memory (128 Kbytes)
multiple byte access read cycle 6-52
multiple byte access write cycle 6-54
single byte access read cycle 6-48
single byte access write cycle 6-50
O
objectives of DMA architecture 2-58
opcode 5-10 , 5-14 , 5-23 , 5-27
fetch burst capability 2-32
operating conditions 6-2
operating register/burst read
32-bit address and data 6-32
64-bit address and data 6-34
operating register/burst write
32-bit address and data 6-36
64-bit address and data 6-38
operating register/SCRIPTS RAM read
32-bits 6-18 , 6-21
operating register/SCRIPTS RAM write
64 bits 6-22
operator 5-23
output current as a function of output voltage 6-10
output signals 6-5
P
PAR 3-6
PAR64 3-7
parallel
protocol request 2-24
ROM 2-58
ROM support 2-59
parity 3-6
control and generation 2-34
error 3-9
(PAR) 4-75
errors and interrupts 2-36
options 2-34
parity64 3-7
PCI
addressing 2-3
bus commands and encoding types 2-5
bus commands and functions supported 2-4
cache line size register 2-9
cache mode 2-11
command register 2-9
commands 2-4
configuration info enable (PCICIE) 4-53
configuration register read 6-16
configuration register write 6-17
configuration registers 4-1
configuration space 2-3
external memory interface timing diagrams 6-14
functional description 2-3
I/O space 2-4
interface signals 3-5
master transaction 2-12
master transfer 2-12
memory space 2-4
performance 1-8
target disconnect 2-10
target retry 2-10
PERR/ 3-9
phase mismatch
handling in SCRIPTS 2-19
jump address one (PMJAD1) 4-115
jump address two (PMJAD2) 4-115
physical longword address and data 3-6
PME
clock (PMEC) 4-19
enable (PEN) 4-20
status (PST) 4-19
support (PMES) 4-18
polling 2-46
power
and ground signals 3-16
management 2-61