Avago Technologies LSI53C1000R User Manual

Page 55

SCSI Functional Description

2-25

Version 2.2

Note:

For DT mode or when the Protocol Options field is nonzero,
the Transfer Width Exponent must be one indicating a SCSI
width of 16 bits.

Note:

The Table Indirect data (used during selection/reselection)
must be updated to enable certain control bits in the
SCNTL4 register. Specific bits to look at include: bit 7,
U3EN (Ultra160 Transfer Enable); bit 6, AIPEN
(Asynchronous Information Protection Enable); and
bits [3:0] (Extra Clock Setup/Hold).

Protocol Options (Byte 7) –

A bus or device reset, power cycle, or change between LVD/SE modes
invalidates these settings. A renegotiation resets the Protocol Options.

2.2.5.3 Asynchronous Information Protection (AIP)

The AIP feature provides error checking for asynchronous, nondata
phases through BCH encoding. During the command, status, message
in/out phases, the BCH code is transferred on the upper SCSI data bus.
For details on the BCH code, refer to T10 119 document “Protection for
the Asynchronous Phases”.

QAS_REQ

DT_REQ

IU_REQ

Description

Use ST Data-In and ST Data-Out phase
to transfer data

Use DT Data-In and DT Data-Out phase
to transfer data with CRC

Use DT Data-In and DT Data-Out phase
to transfer data with information units

Use DT Data-In and DT Data-Out phase
to transfer data with CRC and use the
QAS method for arbitration

Use DT Data-In and DT Data-Out phase
to transfer data with information units and
use the QAS method for arbitration

This manual is related to the following products:

LSI53C1000