Avago Technologies LSI53C1000R - Manual (Page 59)

SCSI Functional Description 2-29
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
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The AIP Control One (AIPCNTL1) register:
– Bits [7:4] are reserved.
– Bit 3, DISAIP (Disable AIP Code Generation), disables the AIP
code generation on the SCSI bus.
– Bit 2, RAIPERR (Reset AIP Error), allows an AIP error condition
to be reset manually.
– Bit 1, FBAIP (Force Bad AIP Value), causes bad AIP values to
be sent over the SCSI bus.
– Bit 0, RSQ (Reset AIP Sequence Value), causes the sequence
value used in the calculation of the protection code to be reset.
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The CRC Pad Byte Value (CRCPAD) register:
– Bits [15:0], the CRC Pad byte value, contain the value placed
onto the bus for the CRC pad bytes.
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The CRC Control Zero (CRCCNTL0) register:
– Bit 7, DCRCC (Disable CRC Checking), is set to cause the
internal logic to not check or report CRC errors during Ultra160
transfers. The device continues to calculate and send CRCs as
requested by the target according to the SPI-3 specification.
– Bit 6, DCRCPC (Disable CRC Protocol Checking) causes the
LSI53C1000R to not check for a CRC request prior to a phase
change on the SCSI bus. This condition creates a SCSI error
condition and makes the device noncompliant with the SPI-3
specification. Do not set these bits under normal operating
conditions.
– Bit 5, RSTCRCINT (Reset CRC Interval Counter) resets the
internal CRC interval counter to zero.
– Bit 4 is reserved.
– Bits [3:0], CRCINT[3:0] (CRC Request Interval (Target Mode only)),
determine when a CRC request is sent by the device when
operating in target mode and transferring data in the DT Data In or
DT Data Out phases.