Avago Technologies LSI53C1000R User Manual
Page 196
4-84
Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
SLT
Selection Response Logic Test
3
This bit is set when the LSI53C1000R is ready to be
selected or reselected. This does not take into account
the bus settle delay of 400 ns. This bit is used for
functional test and fault purposes.
ART
Arbitration Priority Encoder Test
2
This bit is always set when the LSI53C1000R exhibits the
highest priority ID asserted on the SCSI bus during
arbitration. It is primarily used for chip level testing. It may
be used during low level mode operation to determine if
the LSI53C1000R won arbitration.
SOZ
SCSI Synchronous Offset Zero
1
This bit indicates that the current synchronous SREQ/,
SACK/ offset is zero. This bit is not latched and may
change at any time. It is used in low level synchronous
SCSI operations. When this bit is set, and if the
LSI53C1000R is functioning as an initiator, then it is waiting
for the target to request data transfers. When this bit is set,
and if the LSI53C1000R is functioning as a target, then the
initiator has sent the offset number of acknowledges.
SOM
SCSI Synchronous Offset Maximum
0
This bit indicates that the current synchronous SREQ/,
SACK/ offset is the maximum specified by bits [5:0] in the
register. This bit is not latched
and may change at any time. It is used in low level
synchronous SCSI operations. If this bit is set, and if the
LSI53C1000R is functioning as a target, it is waiting for
the initiator to acknowledge the data transfers. If the
LSI53C1000R is functioning as an initiator, the target has
sent the offset number of requests.