Avago Technologies LSI53C1000R User Manual
Page 152
4-40
Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
MDPE
Master Data Parity Error
6
This bit is set when the LSI53C1000R, acting as a PCI
master, detects a data parity error, or, when acting as a
target device, signals a parity error during a data phase.
This bit is completely disabled by the Master Parity Error
Enable bit (bit 3 of
).
BF
Bus Fault
5
This bit is set when a PCI bus fault condition is detected.
A PCI bus fault can only occur when the LSI53C1000R
is bus master, and is defined as a cycle that ends with a
Bad Address or Target Abort Condition.
ABRT
Aborted
4
This bit is set when an abort condition occurs. An abort
condition occurs when a software abort command is
issued by setting bit 7 of the
Interrupt Status Zero (ISTAT0)
register.
SSI
Single Step Interrupt
3
If the Single-Step Mode bit in the
register is set, this bit is set and an interrupt generated
after successful execution of each SCRIPTS instruction.
SIR
SCRIPTS Interrupt Instruction Received
2
This status bit is set whenever an interrupt instruction is
evaluated as true.
R
Reserved
1
IID
Illegal Instruction Detected
0
This status bit is set any time an illegal or reserved
instruction opcode is detected, whether the
LSI53C1000R is operating in single-step mode or
automatically executing SCSI SCRIPTS.
Any of the following conditions during instruction
execution also sets this bit:
•
The LSI53C1000R is executing a Wait Disconnect
instruction and the SCSI REQ line is asserted without
a disconnect occurring.
•
A Block Move instruction is executed as an initiator with
0x000000 loaded into the
register, indicating there are zero bytes to move.