Avago Technologies LSI53C1000R - Manual (Page 78)

2-48 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits before
continuing. The CLF bit is bit 2 in
Chip Test Three (CTEST3) register.
The CSF bit is bit 1 in SCSI Test Three (STEST3) register.
DSTAT – The DMA Status (DSTAT) register contains the status of
DMA-type interrupts whether they are enabled in DIEN or not. Reading
this register determines which condition(s) caused the DMA-type
interrupt, clears any interrupt related bits in DSTAT, and clears the DIP
bit in
Interrupt Status Zero (ISTAT0) . Because the LSI53C1000R stacks
interrupts, reading DSTAT does not necessarily clear the register as
additional interrupts may be pending.
Bit 7 (DFE) in the DMA Status (DSTAT) register, is purely a status bit; it
does not generate an interrupt and is not cleared when read. DMA
interrupts do not flush the DMA or SCSI FIFOs before generating the
interrupt. Therefore, the DFE bit in the DSTAT register should be checked
after any DMA interrupt. If the DFE bit is cleared, the FIFOs must either
be cleared by setting the CLF (Clear DMA FIFO in CTEST3) and
CSF (Clear SCSI FIFO in STEST3) bits, or flushed by setting the
FLF (Flush DMA FIFO in CTEST3) bit.
SIEN0 and SIEN1 – The SCSI Interrupt Enable Zero (SIEN0) and
SCSI Interrupt Enable One (SIEN1) registers are the interrupt enable
registers for the SCSI interrupts in SCSI Interrupt Status Zero (SIST0)
and SCSI Interrupt Status One (SIST1) . Clearing the appropriate mask
bit masks an interrupt.
DIEN – The DMA Interrupt Enable (DIEN) register is the interrupt enable
register for DMA interrupts in DMA Status (DSTAT) . Clearing the
appropriate mask bit masks an interrupt.
2.2.16.3 Fatal vs. Nonfatal Interrupts
A fatal interrupt, as the name implies, always causes the SCRIPTS to stop
running. All nonfatal interrupts become fatal when they are enabled by
setting the appropriate interrupt enable bit. Interrupt masking is discussed
in
Section 2.2.16.4, “Masking.” All DMA interrupts are fatal. The DMA
interrupts are indicated by the DIP bit in Interrupt Status Zero (ISTAT0)
and one or more bits in DMA Status (DSTAT) .