Register: 0x4e – Avago Technologies LSI53C1000R User Manual
Page 198
4-86
Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x4E
SCSI Test Two (STEST2)
Read/Write
SCE
SCSI Control Enable
7
Setting this bit allows assertion of all SCSI control and
data lines through the
SCSI Output Control Latch (SOCL)
and
registers regardless
of whether the LSI53C1000R is configured as a target or
initiator.
Note:
Do not set this bit during normal operation because it could
cause contention on the SCSI bus. It is included for
diagnostic purposes only.
ROF
Reset SCSI Offset
6
Setting this bit clears any outstanding synchronous
SREQ/SACK offset. If a SCSI gross error occurs, set this
bit. This bit automatically clears itself after resetting the
synchronous offset.
Mode
Bits [1:0]
Operation
0
00
If the INT_DIR/ input pin is LOW,
interrupts are signaled on ALT_INTA/.
Otherwise, interrupts are signaled on
both INTA/ and ALT_INTA/.
1
01
Interrupts are only signaled on INTA/,
not ALT_INTA/. The INT_DIR/ input
pin is ignored.
2
10
Interrupts are only signaled on
ALT_INTA/. The INT_DIR/ input pin is
ignored.
3
11
Interrupts are signaled on both INTA/
and ALT_INTA/. The INT_DIR input
pin is ignored.
7
6
5
4
3
2
1
0
SCE
ROF
R
SZM
R
LOW
0
0
0
0
0
0
0
0