Avago Technologies LSI53C1000R - Manual (Page 296)

6-14 Specifications
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
6.4 PCI and External Memory Interface Timing Diagrams
Tables 6.17 through 6.38 and figures 6.11 through 6.34 represent signal
activity when the LSI53C1000R accesses the PCI bus. This section
includes timing diagrams for access to three groups of memory
configurations. The first group applies to Target Timing. The second
group applies to Initiator Timing. The third group applies to
External Memory Timing.
Note: Multiple byte accesses to the external memory bus
increase the read or write cycle by 11 clocks for each
additional byte.
Timing diagrams included in this section are:
•
Target Timing
– PCI Configuration Register Read
– PCI Configuration Register Write
– Operating Registers/SCRIPTS RAM Read, 32 Bits
– Operating Register/SCRIPTS RAM Read, 64 Bits
– Operating Register/SCRIPTS RAM Read, 32 Bits
– Operating Register/SCRIPTS RAM Write, 64 Bits
•
Initiator Timing
– Nonburst Opcode Fetch, 32-Bit Address and Data
– Burst Opcode Fetch, 32-Bit Address and Data
– Back to Back Read, 32-Bit Address and Data
– Back to Back Write, 32-Bit Address and Data
– Burst Read, 32-Bit Address and Data
– Burst Read, 64-Bit Address and Data
– Burst Write, 32-Bit Address and Data
– Burst Write, 64-Bit Address and Data
•
External Memory Timing
– External Memory Read
– External Memory Write