Avago Technologies LSI53C1000R - Manual (Page 203)

SCSI Registers 4-91
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
asynchronous mode. It also writes to the synchronous
data FIFO when testing the chip. The power-up value of
this register is indeterminate.
Register: 0x56
Chip Control Zero (CCNTL0)
Read/Write
ENPMJ Enable Phase Mismatch Jump 7
Upon setting this bit, any phase mismatches do not
interrupt but force a jump to an alternate location to
handle the phase mismatch. Prior to taking the jump, the
appropriate remaining byte counts and addresses are
calculated to facilitate storage.
In the case of a SCSI send, any data in the part is
automatically cleared after being accounted for. In the
case of a SCSI receive, all data is flushed out of the part
and accounted for prior to taking the jump. This feature
does not cover, however, the byte that may appear in
SCSI Wide Residue (SWIDE) . This byte must be flushed
manually.
This bit also enables the flushing mechanism to flush
data during a Data-In phase mismatch in a more efficient
manner.
PMJCTL Jump Control 6
This bit controls which decision mechanism is used when
jumping on phase mismatch. When this bit is cleared, the
LSI53C1000R uses
Phase Mismatch Jump Address One (PMJAD1) when the
WSR bit is cleared and
Phase Mismatch Jump Address Two (PMJAD2) when the
WSR bit is set. When this bit is set, the LSI53C1000R
uses
Phase Mismatch Jump Address One (PMJAD1) on
Data-Out (Data-Out, Command, Message-Out) transfers
and
Phase Mismatch Jump Address Two (PMJAD2) on
Data-In (Data-In, Status, Message-In) transfers. The
7 6 5 4 3 2 1 0
ENPMJ PMJCTL ENNDJ DISFC R DISRC R
0 0 0 0 x x 0 x