Avago Technologies LSI53C1000R - Manual (Page 65)

SCSI Functional Description 2-35
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Enable Parity/CRC/AIP
Error Interrupt SCSI Interrupt
Enable Zero
(SIEN0)
, Bit 0
This bit determines whether the LSI53C1000R
generates an interrupt when it detects a SCSI
parity/CRC/AIP error.
Parity Error SCSI Interrupt
Status Zero (SIST0)
,
Bit 0
This status bit is set whenever the LSI53C1000R
detects a parity/CRC/AIP error on the SCSI bus.
Status of SCSI Parity
Signal SCSI Status Zero
(SSTAT0)
, Bit 0
This status bit represents the active HIGH current state
of the SCSI SDP0 parity signal.
SCSI SDP1 Signal SCSI Status Two
(SSTAT2)
, Bit 0
This bit represents the active HIGH current state of the
SCSI SDP1 parity signal.
Latched SCSI Parity SCSI Status Two
(SSTAT2)
, Bit 3
SCSI Status One
(SSTAT1)
, Bit 3
These bits reflect the SCSI odd parity signal
corresponding to the data latched into the
SCSI Input Data Latch (SIDL) register.
Master Parity Error
Enable Chip Test Four
(CTEST4)
, Bit 3
This bit enables parity checking during PCI master data
phases.
Master Data Parity
Error DMA Status
(DSTAT)
, Bit 6
This bit is set when the LSI53C1000R, as a PCI master,
detects a target device signaling a parity error during a
data phase.
Master Data Parity
Error Interrupt Enable DMA Interrupt
Enable (DIEN)
, Bit 6
By clearing this bit, a Master Data Parity Error does not
cause assertion of INTA/, but the status bit is set in the
DMA Status (DSTAT) register.
AIP Checking Enable SCSI Control Four
(SCNTL4)
, Bit 6
Setting this bit enables the AIP checking of the upper
byte lane of protection information during command,
status, and message phases.
CRC Request OK SCSI Control Zero
(SCNTL0)
, Bit 2
This bit indicates that it is acceptable to force a CRC
request. This bit is set only if a CRC request has been
sent and no data has been transferred since that
request. This bit can determine if it is necessary to send
a CRC request at the end of a data transfer prior to
changing phases in target mode. Use this bit to prevent
back to back CRC conditions.
Disable CRC Checking CRC Control Zero
(CRCCNTL0)
, Bit 7
This bit is set to cause internal logic not to check or
report CRC errors during Ultra160 transfers.
Disable CRC Protocol
Checking CRC Control Zero
(CRCCNTL0)
, Bit 6
This bit is set to cause the device not to check for a
CRC request prior to a phase change on the SCSI bus.
This condition normally causes a SCSI error condition.
Note: Setting this bit makes the LSI53C1000R
noncompliant to the SPI-3 specification. Do not set this
bit under normal operating conditions.
Table 2.4 Bits Used for Parity/CRC/AIP Control and Generation (Cont.)
Bit Name Location Description