beautypg.com

Avago Technologies LSI53C1000R User Manual

Page 376

background image

IX-4

Index

(VP)

5-32

(VUE0)

4-30

(VUE1)

4-30

(WATN)

4-25

(WIE)

4-4

(WOA)

4-43

(WRIE)

4-55

(WSR)

4-30

(WSS)

4-30

Numerics

32/64-bit jump

5-31

32-bit addressing

5-6

3-state

3-2

64 Kbytes ROM read cycle

6-60

64 Kbytes ROM write cycle

6-61

64-bit

addressing

5-8

addressing in SCRIPTS

2-21

table indirect indexing mode (64TIMOD)

4-93

A

A and B DIFFSENS SCSI signals

6-4

A[6:0]

5-24

A_DIFFSENS

3-11

A_GPIO0

3-13

A_GPIO1

3-13

A_GPIO2

3-13

A_GPIO3

3-13

A_GPIO4

3-13

A_SACK+-

3-12

A_SATN+-

3-12

A_SBSY+-

3-12

A_SC_D+-

3-12

A_SD[15:0]+-

3-10

A_SDP[1:0]+-

3-10

A_SI_O+-

3-12

A_SMSG+-

3-12

A_SREQ+-

3-12

A_SRST+-

3-12

A_SSEL+-

3-12

abort operation (ABRT)

4-46

aborted (ABRT)

4-40

,

4-65

absolute maximum stress ratings

6-2

AC characteristics

6-11

ACK64/

3-7

acknowledge 64

3-7

active termination

2-39

AD[63:0]

3-6

adder sum output (ADDER)

4-69

address and data signals

3-6

address/data bus

2-3

AIP

1-4

,

2-25

control and generation

2-34

enable

4-101

options

2-34

alt interrupt

3-9

ALT_INTA/

3-9

arbitration

in progress (ARBIP)

4-42

mode bits 1 and 0 (ARB[1:0])

4-23

priority encoder test (ART)

4-84

signals

3-8

assert

even SCSI parity (force bad parity) (AESP)

4-28

SATN/ on parity/CRC error (AAP)

4-26

SCSI

ACK/ signal (ACK)

4-37

,

4-39

ATN/ signal (ATN)

4-37

,

4-39

BSY/ signal (BSY)

4-37

,

4-39

C_D/ signal (C_D)

4-37

,

4-39

data bus (ADB)

4-27

I_O/ signal (I_O)

4-37

,

4-39

MSG/ signal (MSG)

4-37

,

4-39

REQ/ signal (REQ)

4-37

,

4-39

RST/ signal (RST)

4-28

SEL/ signal (SEL)

4-37

,

4-39

asynchronous information protection

2-25

enable

4-101

asynchronous SCSI

receive

2-38

send

2-37

aux_current

4-19

B

back to back read,

32-bit address and data

6-28

back to back write

32-bit address and data

6-30

base address register

four (BAR4[31:0])

4-11

one (BAR1[31:0])

2-4

,

4-9

three (BAR3[31:0])

4-10

two (BAR2[31:0])

4-10

zero - I/O (BAR0[31:0])

2-4

,

4-9

BCH

2-25

bidirectional

3-2

signals

6-5

,

6-6

BIOS

2-3

bits used for parity control and generation

2-34

block move

2-10

instructions

5-4

bridge support extensions (BSE[7:0])

4-20

This manual is related to the following products: