Avago Technologies LSI53C1000R User Manual
Page 376

IX-4
Index
(VP)
(VUE0)
(VUE1)
(WATN)
(WIE)
(WOA)
(WRIE)
(WSR)
(WSS)
Numerics
32/64-bit jump
32-bit addressing
3-state
64 Kbytes ROM read cycle
64 Kbytes ROM write cycle
64-bit
addressing
addressing in SCRIPTS
table indirect indexing mode (64TIMOD)
A
A and B DIFFSENS SCSI signals
A[6:0]
A_DIFFSENS
A_GPIO0
A_GPIO1
A_GPIO2
A_GPIO3
A_GPIO4
A_SACK+-
A_SATN+-
A_SBSY+-
A_SC_D+-
A_SD[15:0]+-
A_SDP[1:0]+-
A_SI_O+-
A_SMSG+-
A_SREQ+-
A_SRST+-
A_SSEL+-
abort operation (ABRT)
aborted (ABRT)
absolute maximum stress ratings
AC characteristics
ACK64/
acknowledge 64
active termination
AD[63:0]
adder sum output (ADDER)
address and data signals
address/data bus
AIP
control and generation
enable
options
alt interrupt
ALT_INTA/
arbitration
in progress (ARBIP)
mode bits 1 and 0 (ARB[1:0])
priority encoder test (ART)
signals
assert
even SCSI parity (force bad parity) (AESP)
SATN/ on parity/CRC error (AAP)
SCSI
ACK/ signal (ACK)
ATN/ signal (ATN)
BSY/ signal (BSY)
C_D/ signal (C_D)
data bus (ADB)
I_O/ signal (I_O)
,
MSG/ signal (MSG)
,
REQ/ signal (REQ)
,
RST/ signal (RST)
SEL/ signal (SEL)
asynchronous information protection
enable
asynchronous SCSI
receive
send
aux_current
B
back to back read,
32-bit address and data
back to back write
32-bit address and data
base address register
four (BAR4[31:0])
one (BAR1[31:0])
,
three (BAR3[31:0])
two (BAR2[31:0])
zero - I/O (BAR0[31:0])
BCH
bidirectional
signals
BIOS
bits used for parity control and generation
block move
instructions
bridge support extensions (BSE[7:0])