Avago Technologies LSI53C1000R - Manual (Page 57)

SCSI Functional Description 2-27
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
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The SCSI Control Three (SCNTL3) register:
– Bit 7 is now reserved. It was previously the Ultra Enable bit.
– Bits [6:4], SCF[2:0] (Synchronous Clock Conversion Factor),
select the divisor of the SCLK frequency. The SCLK is divided
before its presentation to the synchronous SCSI control logic.
– Bit 3, EWS (Enable Wide SCSI), is set to enable wide SCSI.
Ultra160 requires wide SCSI. Therefore, this bit must be set
during these transfers.
– Bits [2:0] are reserved.
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The SCSI Transfer (SXFER) register:
– Bits [7:6] are reserved.
– Bits [5:0], MO[5:0] (Max SCSI synchronous offset), are set for
the maximum offset.
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The SCSI Status Two (SSTAT2) register:
– Bit 2 is reserved. HVD SCSI is not supported.
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The SCSI Interrupt Enable Zero (SIEN0) register:
– Bit 0, PAR (SCSI Parity/CRC/AIP Error), is set to detect a
parity/CRC/AIP error while receiving or sending SCSI data. For
more information, refer to
SCSI Control One (SCNTL1) , bit 5.
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The Chip Control Three (CCNTL3) register:
– Bit 4, ENDSKEW (Enable REQ/ACK to Data skew control) is set
to enable control of the relative skew between the SCSI
REQ/ACK signal and the data signals.
– Bits [3:2], DSKEW[1:0] (REQ/ACK – Data skew control), control
the amount of skew between the SCSI REQ/ACK signal and the
SCSI data signals. These bits are used for Ultra160 SCSI
Domain Validation only and control the skew only if bit 4 is set.
– Bits [1:0], LVDDL[1:0] (LVD Drive strength select), control the
drive level of the LVD pad drivers. This feature is intended for use
in Ultra160 SCSI Domain Validation testing environments only.
Set these bits to 0b00 during normal operation.