Avago Technologies LSI53C1000R - Manual (Page 178)

4-66 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x3A
Scratch Byte Register (SBR)
Read/Write
SBR Scratch Byte Register [7:0]
This is a general purpose register. Apart from CPU
access, only register Read/Write and Memory Moves into
this register alter its contents. The default value of this
register is zero. This register is called the DMA
Watchdog Timer on previous LSI53C8XX family products.
Register: 0x3B
DMA Control (DCNTL)
Read/Write
CLSE Cache Line Size Enable 7
Setting this bit enables the LSI53C1000R to sense and
react to cache line boundaries set up by the
DMA Mode (DMODE) or PCI Cache Line Size (CLS)
register, whichever contains the smaller value. Clearing
this bit disables the cache line size logic.
PFF Prefetch Flush 6
Setting this bit causes the prefetch unit to flush its
contents. This bit clears after the flush is complete.
PFEN Prefetch Enable 5
Setting this bit enables an 8 Dword SCRIPTS instruction
prefetch unit. The prefetch unit, when enabled, fetches
8 Dwords of instructions and instruction operands in
bursts of 4 or 8 Dwords. Prefetching instructions allows
the LSI53C1000R to make more efficient use of the
system PCI bus, thus improving overall system
performance. A flush occurs whenever the PFF bit is set,
on all transfer control instructions (when the transfer
7 0
SBR
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
CLSE PFF PFEN SSM IRQM STD R COM
0 0 0 0 0 0 0 0