Avago Technologies LSI53C1000R User Manual

Page 138

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Registers

Version 2.2

can determine if it is necessary to send a CRC request
at the end of a data transfer, prior to changing phases in
target mode. This bit may prevent back-to-back CRC
conditions. Back-to-back CRC requests are illegal.

AAP

Assert SATN/ on Parity/CRC/AIP Error

When this bit is set, the LSI53C1000R automatically
asserts the SATN/ signal upon detection of a parity error
or CRC error. SATN/ is only asserted in the initiator mode.
The SATN/ signal is asserted before deasserting SACK/
during the byte transfer with the parity error. Also set the
Enable Parity/CRC/AIP Checking bit for the LSI53C1000R
to assert SATN/ in this manner. A parity error or CRC
error is detected on data received from the SCSI bus.

If the Assert SATN/ on Parity/CRC/AIP Error bit is cleared
or the Enable Parity/CRC/AIP Checking bit is cleared,
SATN/ is not automatically asserted on the SCSI bus
when a Parity/CRC/AIP error is received.

TRG

Target Mode

This bit determines the default operating mode of the
LSI53C1000R. The user must manually set the target or
initiator mode. This is done using the SCRIPTS language
(

SET TARGET

CLEAR TARGET

). When this bit is set, the

chip is a target device. When this bit is cleared, the
LSI53C1000R is an initiator device.

Caution:

Writing this bit while not connected may cause the loss of
a selection or reselection due to the changing of target or
initiator modes.

This manual is related to the following products:

LSI53C1000