Avago Technologies LSI53C1000R - Manual (Page 90)

2-60 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.4 Serial EEPROM Interface
The LSI53C1000R implements an interface permitting attachment of a
serial EEPROM device to the GPIO[0] and GPIO[1] pins. There are two
modes of operation relating to the serial EEPROM, the
Subsystem ID (SID)
register, and the Subsystem Vendor ID (SVID) register. These modes are
programmable through the MAD[7] pin, which is sampled at power-up.
2.4.1 Default Download Mode
In this mode, MAD[7] is pulled down internally, GPIO[0] is the serial data
signal (SDA) and GPIO[1] is the serial clock signal (SCL). Certain data in
the serial EEPROM is automatically loaded into chip registers at power-up.
The format of the serial EEPROM data is defined in Table 2.8 . If the
download is enabled and an EEPROM is not present or the checksum
fails, the
Subsystem ID (SID) and Subsystem Vendor ID (SVID) registers
read back all zeros. At power-up five bytes are loaded into the chip from
locations 0xFB through 0xFF.
The Subsystem ID (SID) and Subsystem Vendor ID (SVID) registers are
read only in accordance with the PCI specification, with a default value
of all zeros if the download fails.
Note: The speed of the serial EEPROM must be 400 Kbits/s.