Avago Technologies LSI53C1000R - Manual (Page 56)

2-26 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
The AIP error status and the live AIP code values are captured in the
AIP Control Zero (AIPCNTL0) register for debug purposes. AIP checking
is enabled by setting bit 6 in the SCSI Control Four (SCNTL4) register.
AIP generation occurs by default and may be disabled by setting bit 3,
Disable AIP Code Generation, in
AIP Control One (AIPCNTL1) .
The sequence ID is reset on any phase change, chip reset, bus free, or
synchronous phase. It is also reset by writing the RSQAIP bit in the
AIP Control One (AIPCNTL1) register. The AIP sequence value can be
read using this register (SEQAIP).
All AIP errors are treated in the same fashion as parity errors. Bit 0 of the
SCSI Interrupt Status Zero (SIST0) register indicates if SCSI parity, CRC,
or AIP errors are present. The AIPERR bit in the
AIP Control Zero (AIPCNTL0) register indicates if the error is an AIP error.
2.2.5.4 Register Considerations
The following is a summary of the registers and bits required to enable
Ultra160 SCSI on the LSI53C1000R.
•
The PCI Device ID register value must be 0x21.
•
The PCI Max_Lat (ML) register contains a value of 0x12, indicating
it requires the bus every 4.5
µ
s.
•
The SCSI Control Zero (SCNTL0) register:
– Bit 3, EPC (Enable Parity/CRC/AIP Checking) is set to enable
the CRC feature.
– Bit 1, AAP (Assert SATN/ on Parity/CRC/AIP Error), is set in the
initiator mode to assert SATN/ automatically on the detection of
an error.
•
The SCSI Control One (SCNTL1) register:
– Bit 5, DHP (Disable Halt on Parity/CRC/AIP Error or ATN)
(Target Only), is set in accordance with user requirements. When
bit 5 is cleared, a SCSI transfer halts if an error occurs. When
bit 5 is set, a SCSI transfer continues if an error occurs.