Avago Technologies LSI53C1000R - Manual (Page 166)

4-54 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
When it is set, MMWS contains bits [63:32] and
SCRATCH B contains bits [31:0] of the RAM Base Address
value from the PCI Configuration
Base Address Register Three (BAR3) (SCRIPTS RAM)
and Base Address Register Four (BAR4) (SCRIPTS RAM) .
This is the base address for the 8 Kbytes of internal RAM.
Memory Move Read Selector (MMRS) contains
bits [63:32] and Scratch Register A (SCRATCHA)
contains bits [31:0] of the memory mapped operating
register base address. Bits [23:16] of
SCRIPT Fetch Selector (SFS) contain the PCI
Revision ID (RID) register value and bits [15:0] contain
the PCI Device ID register value. When this bit is set, only
reads to the registers are affected, writes occur normally.
When this bit is cleared, the SCRATCH A, MMRS,
SCRATCH B, MMWS, and SFS registers return to normal
operation.
Note: Bit 3 is the only writable bit in this register. All other bits are
read only. When modifying this register, all other bits must
be written to zero. Do not execute a Read-Modify-Write to
this register.
R Reserved [2:0]
Register: 0x1B
Chip Test Three (CTEST3)
Read/Write
R Reserved [7:4]
FLF Flush DMA FIFO 3
When this bit is set, data residing in the DMA FIFO is
transferred to memory, starting at the address in the
DMA Next Address (DNAD) register. This bit is not
self-clearing; clear it once the data is successfully
transferred by the LSI53C1000R.
Note: Polling of FIFO flags is allowed during flush operations.
7 4 3 2 1 0
R FLF CLF R WRIE
0 0 0 0 0 0 0 0