Avago Technologies LSI53C1000R - Manual (Page 378)

IX-6 Index
DIEN 2-48
differential mode 2-39
DIP 2-51
direct 5-20
disable
auto FIFO clear (DISFC) 4-92
CRC checking 4-121
CRC protocol checking 4-121
dual address cycle (DDAC) 4-93
halt on parity/CRC error or ATN (target only) (DHP)
4-27
single initiator response (DSI) 4-88
disable internal SCRIPTS RAM cycles 4-92
disconnect 2-18
instruction 5-15
DMA
byte counter (DBC) 4-59
command (DCMD) 4-60
control (DCNTL) 2-7 , 2-8 , 2-9 , 2-48 , 4-66
FIFO 2-9 , 2-36 , 2-47
(DF[7:0]) 4-58
empty (DFE) 4-39
sections 2-36
interrupt 2-51
enable (DIEN) 2-35 , 2-48 , 4-65
interrupt pending (DIP) 4-49
mode (DMODE) 2-7 , 2-8 , 2-9 , 2-12 , 2-32 , 4-62
next address (DNAD) 4-60
next address 64 (DNAD64) 4-100
SCRIPTS
pointer (DSP) 4-61
pointer save (DSPS) 4-61
status (DSTAT) 2-35 , 2-48 , 2-50 , 2-51 , 2-52 , 4-39
domain validation 1-5 , 2-22
double transition
clocking 2-23
download mode 2-61
DSA
relative 5-39
relative selector (DRS) 4-99
DSPS register 5-36
DSTAT 2-48
DT data-in 2-23
DT data-out 2-23
DT transfers configuration 2-44
dual address cycles 2-21
command 2-8
dynamic block move selector (DBMS) 4-100
E
EEPROM 2-60
default download mode 2-60
enable
64-bit
table indirect BMOV (EN64TIBMV) 4-94
AIP 4-101
asynchronous information protection 4-101
bus mastering (EBM) 4-4
I/O space (EIS) 4-4
jump on nondata phase mismatches (ENNDJ) 4-92
memory space (EMS) 4-4
parity
checking (EPC) 2-34 , 4-25
error response (EPER) 4-3
phase mismatch jump (ENPMJ) 4-91
read
line (ERL) 4-64
multiple (ERMP) 4-64
response to
reselection (RRE) 4-32
selection (SRE) 4-32
wide SCSI (EWS) 4-31
enable 64-bit
direct BMOV (EN64DBMV) 4-94
ENABLE66 3-5
enabling cache mode 2-12
encoded
chip SCSI ID (ENC[3:0]) 4-32
destination SCSI ID
(ENC[3:0]) 4-34
(ENID[3:0]) 4-38
SCSI destination ID 5-21
entry storage address (ESA) 4-118
error reporting signals 3-8
even parity 2-34
expansion ROM base address 4-14
external
clock 6-11
memory
configuration 2-59
diagram examples B-1
multiple byte accesses 6-14
read 6-41
timing 6-41
write 6-45
F
fast back to back capable 4-6
fatal interrupt 2-48
fetch enable (FE) 4-78
FIFO
byte control (FBL[2:0]) 4-56
byte control (FBL3) 4-56
first dword 5-4 , 5-14 , 5-23 , 5-27 , 5-39