14 select/reselect during selection/reselection, 15 synchronous operation, Select/reselect during selection/reselection – Avago Technologies LSI53C1000R User Manual
Page 71: Synchronous operation
SCSI Functional Description
2-41
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.2.14 Select/Reselect during Selection/Reselection
In multithreaded SCSI I/O environments, it is not uncommon to be
selected or reselected while trying to perform selection/reselection. This
situation may occur when a SCSI controller (operating in the initiator
mode) tries to select a target and is reselected by another. The
Select SCRIPTS instruction has an alternate address to which the
SCRIPTS jumps when this situation occurs. The analogous situation for
target devices is being selected while trying to perform a reselection.
When a change in operating mode occurs, either the initiator SCRIPTS
issues a Set Initiator instruction or the target SCRIPTS issues a
Set Target instruction. The Selection and Reselection Enable bits
(
bits 5 and 6, respectively) should both be asserted,
enabling the LSI53C1000R to respond as an initiator or as a target. If
only selection is enabled, the LSI53C1000R cannot be reselected as an
initiator. Status bits, in the
SCSI Interrupt Status Zero (SIST0)
register,
and interrupt bits, in the
SCSI Interrupt Enable Zero (SIEN0)
register,
indicate if the LSI53C1000R has been selected or reselected.
2.2.15 Synchronous Operation
The LSI53C1000R can transfer synchronous SCSI data in both the
initiator and target modes. The LSI53C1000R’s SCLK input must be
connected to a 40 MHz oscillator. The
register
controls the synchronous offset while the
register controls the synchronous clock converters. These registers may
be loaded by the CPU before SCRIPTS execution begins, from within
SCRIPTS, with a Table Indirect I/O instruction, or with a
Read-Modify-Write instruction.
The LSI53C1000R can receive data from the SCSI bus at a synchronous
transfer period as short as 12.5 ns, regardless of the transfer period that
sends data. The LSI53C1000R can receive data at one-fourth of the
divided SCLK frequency. Depending on the SCLK frequency, the
negotiated transfer period, and the synchronous clock divider, the
LSI53C1000R can send synchronous data at intervals as short as
12.5 ns for Ultra160 SCSI, 25 ns for Ultra2 SCSI, 50 ns for Ultra SCSI,
100 ns for Fast SCSI, and 200 ns for SCSI-1.
Synchronous data transfer rates are controlled by bits in two different
registers of the LSI53C1000R. Following is a brief description of these
bits and the method that determines the data transfer rate.