Crc data (crcd), Registers: 0xe4–0xe7 – Avago Technologies LSI53C1000R User Manual
Page 234
4-122
Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
R
Reserved
6
ENAS
Enable CRC Auto Seed
5
Setting this bit causes the CRC logic to reseed
automatically after every CRC check performed during
DT Data-In SCSI transfers. When this bit is cleared, the
SCSI control logic controls when the reseeding occurs.
TSTSD
Test CRC Seed
4
Setting this bit causes the CRC logic to reseed itself
immediately. This bit should never be set during normal
operation because it may cause corrupt CRCs to be
generated.
TSTCHK
Test CRC Check
3
Setting this bit causes the CRC logic to initiate a CRC
check. This bit should never be set during normal
operation because it results in spurious CRC errors.
TSTADD
Test CRC Accumulate
2
Setting this bit causes the CRC block to take the value in
its input register and add it into the current CRC
calculation, resulting in a new output CRC value. This bit
should not be set during normal operation because it
results in corrupt CRC values.
CRCDSEL
CRC Data Register Selector
[1:0]
These bits control the data that is visible in the
register.
Registers: 0xE4–0xE7
CRC Data (CRCD)
Read/Write
The value in this register is dependent on the setting of the CRCDSEL
bits in the
register.
Note:
Data written to this register may not be available for
immediate read back due to synchronization between the
PCI and SCSI clock domains. After a write, wait at least
16 PCI clock cycles before reading this register.
31
0
CRCD
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x