Avago Technologies LSI53C1000R - Manual (Page 261)

I/O Instructions 5-19
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
TI Table Indirect Mode 25
When this bit is set, the 24-bit signed value in the
DMA Byte Counter (DBC) register is added to the value in
the Data Structure Address (DSA) register, and used as an
offset relative to the value in the Data Structure Address
(DSA) register. The
SCSI Control Three (SCNTL3) value,
SCSI ID, synchronous offset, and synchronous period are
loaded from this address. Prior to the start of an I/O, load
the
Data Structure Address (DSA) with the base address
of the I/O data structure. Any address on a Dword
boundary is allowed. After a Table Indirect opcode is
fetched, the
Data Structure Address (DSA) is added to the
24-bit signed offset value from the opcode to generate the
address of the required data. Both positive and negative
offsets are allowed. A subsequent fetch from that address
brings the data values into the chip.
SCRIPTS can directly execute operating system I/O data
structures, saving time at the beginning of an I/O operation.
The I/O data structure can begin on any Dword boundary
and may cross system segment boundaries. There are two
restrictions on the placement of data in system memory:
•
The I/O data structure must lie within the 8 Mbytes
above or below the base address.
•
An I/O command structure must have all four bytes
contiguous in system memory, as follows. The
offset/period bits are ordered as in the
SCSI Transfer (SXFER) register. The configuration bits
are ordered as in the SCSI Control Three (SCNTL3)
register.
Use this bit only in conjunction with the Select, Reselect,
Wait Select, and Wait Reselect instructions. It is allowable
to set bits 25 and 26 individually or in combination:
Config ID Offset/period 00
Bit 25 Bit 26
Direct 0 0
Table Indirect 0 1
Relative 1 0
Table Relative 1 1