Avago Technologies LSI53C1000R - Manual (Page 36)

2-6 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.1.2.3 I/O Read Command
The LSI53C1000R uses the I/O Read command to read data from an
agent mapped in the I/O address space. When decoding I/O cycles, the
LSI53C1000R decodes the lower 32 address bits and ignores the upper
32 address bits.
2.1.2.4 I/O Write Command
The LSI53C1000R uses the I/O Write command to write data to an agent
mapped in the I/O address space. When decoding I/O cycles, the
LSI53C1000R decodes the lower 32 address bits and ignores the upper
32 address bits.
2.1.2.5 Reserved Command
The given bus encoding is reserved.
2.1.2.6 Memory Read Command
The LSI53C1000R uses the Memory Read command to read data from
an agent mapped in the Memory Address Space. The target may
perform an anticipatory read if such a read produces no side effects.
2.1.2.7 Memory Write Command
The LSI53C1000R uses the Memory Write command to write data to an
agent mapped in the Memory Address Space. When the target returns
“ready”, it assumes responsibility for data coherency, which
includes ordering.
2.1.2.8 Configuration Read Command
The Configuration Read command reads the configuration space of a
device. The LSI53C1000R never generates this command as a master,
but does respond to it as a slave. A device on the PCI bus selects the
LSI53C1000R by asserting its IDSEL signal when AD[1:0] are 0b00.
During the address phase of a configuration cycle, AD[7:2] address one
of the 64 Dword registers in the configuration space of each device.
C_BE[3:0]/ address the individual bytes within each Dword. AD[10:8]
indicate which device on the LSI53C1000R is being addressed. The
LSI53C1000R treats AD[63:11] as logical don’t cares.