Avago Technologies LSI53C1000R - Manual (Page 258)

5-16 SCSI SCRIPTS Instruction Set
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
If reselected, the LSI53C1000R fetches the next
instruction from the address pointed to by the 32-bit jump
address field stored in the
DMA Next Address (DNAD)
register. Manually set the LSI53C1000R to the initiator
mode when it is reselected.
If the CPU sets the SIGP bit in the
Interrupt Status Zero (ISTAT0) register, the LSI53C1000R
aborts the Wait Select instruction and fetches the next
instruction from the address pointed to by the 32-bit jump
address field stored in the
DMA Next Address (DNAD)
register.
Set Instruction
When the SACK/ or SATN/ bits are set, the corresponding
bits in the
SCSI Output Control Latch (SOCL) register are
set. Do not set SACK/ or SATN/ except for testing
purposes. When the target bit is set, the corresponding
bit in the
SCSI Control Zero (SCNTL0) register is also
set. When the carry bit is set, the corresponding bit in the
Arithmetic Logic Unit (ALU) is set.
Note: None of the signals are set on the SCSI bus in target mode.
Clear Instruction
When the SACK/ or SATN/ bits are cleared, the
corresponding bits are cleared in the
SCSI Output Control Latch (SOCL) register. Do not set
SACK/ or SATN/ except for testing purposes. When the
target bit is cleared, the corresponding bit in the
SCSI Control Zero (SCNTL0) register is cleared. When
the carry bit is cleared, the corresponding bit in the ALU
is cleared.
Note: None of the signals are cleared on the SCSI bus in the
target mode.