Avago Technologies LSI53C1000R - Manual (Page 131)

PCI Configuration Registers 4-19
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
D2S D2_Support 10
The LSI53C1000R sets this bit to indicate support for
power management state D2. Bits 9 and 10 are set to
one, indicating support for the D1 and D2 power states.
D1S D1_Support 9
The LSI53C1000R sets this bit to indicate support for
power management state D1. Bits 9 and 10 are set to
indicate support for the D1 and D2 power states.
AUX_C Aux_Current [8:6]
The LSI53C1000R always returns zeros. This feature is
not supported.
DSI Device Specific Initialization 5
This bit is cleared to indicate that the LSI53C1000R
requires no special initialization before the generic class
device driver is able to use it.
R Reserved 4
PMEC PME Clock 3
Bit 3 is cleared because the LSI53C1000R does not
provide a PME pin.
VER[2:0] Version [2:0]
These three bits are set to 0b010 to indicate that the
LSI53C1000R complies with Revision 1.1 of the PCI
Power Management Interface Specification.
Registers: 0x44–0x45
Power Management Control/Status (PMCSR)
Read/Write
PST PME_Status 15
The LSI53C1000R always returns a zero for this bit,
indicating that PME signal generation is not supported
from D3cold.
15 14 13 12 9 8 7 2 1 0
PST DSCL DSLT PEN R PWS[1:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0