Avago Technologies LSI53C1000R - Manual (Page 48)

2-18 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.1.3.6 Memory-to-Memory Moves
Memory-to-Memory moves also support PCI cache commands, as
described above, with one limitation: Memory Write and Invalidate on
Memory-to-Memory Move writes are only supported if the source and
destination address are quad word aligned. If the source and destination
are not quad word aligned, that is, Source Address[2:0] ==
Destination Address[2:0], write alignment is not performed and
Memory Write and Invalidates are not issued.
The LSI53C1000R is little endian. This mode assigns the least significant
byte to bits [7:0].
2.2 SCSI Functional Description
The Ultra160 SCSI controller on the LSI53C1000R supports either an
8-bit or 16-bit SCSI bus. The controller supports Wide Ultra160 SCSI
synchronous transfer rates up to 160 Mbytes/s on an LVD SCSI bus. The
LSI53C1000R can be programmed with SCSI SCRIPTS, making it easy
to “fine tune” the system for specific mass storage devices or Ultra160
SCSI requirements.
Figure 2.1 on page 2-2 illustrates the relationship
between the LSI53C1000R modules.
The LSI53C1000R offers low level register access or a high level control
interface. Like first generation SCSI devices, the LSI53C1000R is accessed
as a register-oriented device. The ability to sample and/or assert any signal
on the SCSI bus is used in error recovery and diagnostic procedures.
The LSI53C1000R is controlled by the integrated SCRIPTS processor
through a high level logical interface. Commands controlling the SCSI
function are fetched out of the main host memory or local memory. These
commands instruct the SCSI function to Select, Reselect, Disconnect,
Wait for a Disconnect, Transfer Information, Change Bus Phases, and
implement all other aspects of the SCSI protocol. The SCRIPTS
processor is a special high-speed processor optimized for SCSI protocol.