Scsi status zero (sstat0), Register: 0x0d – Avago Technologies LSI53C1000R User Manual
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Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x0D
SCSI Status Zero (SSTAT0)
Read Only
ILF
SIDL Least Significant Byte Full
7
This bit is set when the least significant byte in the
contains data. Data is
transferred from the SCSI bus to the SCSI Input Data
Latch register before being sent to the DMA FIFO and then
to the host bus. The
register
contains SCSI data received asynchronously. Synchronous
data received does not flow through this register.
R
Reserved
6
OLF
SODL Least Significant Byte Full
5
This bit is set when the least significant byte in the
contains data. The
SODL register is the interface between the DMA logic
and the SCSI bus for asynchronous send operations. In
the asynchronous mode, data is transferred from the host
bus to the SODL register, and then to the SCSI bus. It is
possible to use this bit to determine how many bytes
reside in the device when an error occurs.
ARBIP
Arbitration in Progress
4
Arbitration in Progress (ARBIP = 1) indicates that the
LSI53C1000R has detected a Bus Free condition, asserted
SBSY, and asserted its SCSI ID onto the SCSI bus.
LOA
Lost Arbitration
3
When set, LOA indicates that the LSI53C1000R has
detected a bus free condition, arbitrated for the SCSI bus,
and lost arbitration due to another SCSI device asserting
the SSEL/ signal.
7
6
5
4
3
2
1
0
ILF
R
OLF
ARBIP
LOA
WOA
RST
SDP0
0
0
0
0
0
0
0
0