Avago Technologies LSI53C1000R - Manual (Page 380)

IX-8 Index
on the fly 5-31
on the fly (INTF) 4-48
on the fly instruction 5-29
output 6-13
pin (IP[7:0]) 4-16
polling 2-46
registers 2-46
DIEN 2-48
DSTAT 2-48
ISTAT 2-46
SIEN0 2-48
SIEN1 2-48
SIST0 2-47
SIST1 2-47
request 2-46
routing mode (IRM[1:0]) 4-85
sample interrupt service routine 2-52
stacked 2-50
status one (ISTAT1) 2-46 , 4-50
status zero (ISTAT0) 2-46 , 4-46
interrupts 2-48 , 2-53
nonfatal 2-48
IRDY/ 3-7
IRQ mode (IRQM) 4-67
issuing cache commands 2-12
ISTAT 2-46
J
JTAG boundary scan testing 2-33
jump
address 5-33
call a relative address 5-30
call an absolute address 5-30
control (PMJCTL) 4-91
if true/false 5-31
instruction 5-27
JUMP64 address 5-33
L
last disconnect (LDSC) 4-45
latched SCSI parity
(SDP0L) 4-43
for SD[15:8] (SPL1) 4-45
latency 2-10
timer (LT[7:0]) 4-8
LED 2-21
LED_CNTL (LEDC) 4-78
little endian 2-18
load and store
instructions 2-33 , 5-37
prefetch unit and store instructions 2-32
load/store 5-39
lost arbitration (LOA) 4-42
LSI53C1000R
456 BGA mechanical drawing 6-78
register map A-1 , A-3
LVD 2-39
driver SCSI signals 6-3
receiver SCSI signals 6-3
LVD Link 1-2 , 1-5 , 2-39
benefits 1-5
M
M66EN 3-5
MAD bus programming 3-17
MAD pin decoding 3-18
MAD[0] 3-18
MAD[3:1] 3-18
MAD[4] 3-18
MAD[5] 3-18
MAD[6] 3-18
MAD[7:0] 3-14 , 3-17
MAD[7] 3-18
mailbox one (MBOX1) 2-46 , 4-51
mailbox zero (MBOX0) 2-46 , 4-51
manual start mode (MAN) 4-64
MAS0/ 3-14
MAS1/ 3-14
masking 2-49
master
data parity error (MDPE) 4-40 , 4-65
enable (ME) 4-78
parity error enable (MPEE) 4-56
max SCSI synchronous offset (MO[5:0]) 4-33
max_lat (ML[7:0]) 4-17
maximum stress ratings 6-2
MCE/ 3-14
memory
address strobe 0 3-14
address strobe 1 3-14
address/data bus 3-14
chip enable 3-14
I/O address/DSA offset 5-40
move 2-10
move instructions 2-32 , 5-34
no flush option 2-32
move read selector (MMRS) 4-97 , 4-128
move write selector (MMWS) 4-98 , 4-128
output enable 3-14
read 2-12 , 2-13
read caching 2-13
read command 2-6
read line 2-12 , 2-13
read line command 2-8