Avago Technologies LSI53C1000R - Manual (Page 350)

6-68 Specifications
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
t
DT5
Receive data setup to SREQ/ transition 5 – ns
t
DT6
Receive data hold from SREQ/ transition 5 – ns
t
DT7
Send CRC Request Setup to SREQ/ transition 30 – ns
t
DT8
Send CRC Request Hold to SREQ/ transition 20 – ns
t
DT9
Receive CRC Request Setup to SREQ/ transition 12 – ns
t
DT10
Receive CRC Request Hold to SREQ/ transition 5 – ns
Table 6.48 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or
40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock (Cont.)
Symbol Parameter Min Max Unit
Table 6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or
80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock
Symbol Parameter Min Max Unit
t
DT1
Send SREQ/ assertion pulse width 23 – ns
t
DT2
Send SREQ/ deassertion pulse width 23 – ns
t
DT1
Receive SREQ/ assertion pulse width 20 – ns
t
DT2
Receive SREQ/ deassertion pulse width 20 – ns
t
DT3
Send data setup to SREQ/ transition 10 – ns
t
DT4
Send data hold from SREQ/ transition 10 – ns
t
DT5
Receive data setup to SREQ/ transition 2.5 – ns
t
DT6
Receive data hold from SREQ/ transition 2.5 – ns
t
DT7
Send CRC Request Setup to SREQ/ transition 20 – ns
t
DT8
Send CRC Request Hold to SREQ/ transition 10 – ns
t
DT9
Receive CRC Request Setup to SREQ/ transition 9.5 – ns
t
DT10
Receive CRC Request Hold to SREQ/ transition 2.5 – ns