Instruction address (ia), Scsi byte count (sbc), Registers: 0xd4–0xd7 – Avago Technologies LSI53C1000R User Manual

Page 231: Registers: 0xd8–0xda

SCSI Registers

4-119

Version 2.2

Registers: 0xD4–0xD7

Instruction Address (IA)
Read/Write

Instruction Address

[31:0]

This register always contains the address of the BMOV
instruction that was executing when the phase mismatch
occurred. This value always matches the value in the

Entry Storage Address (ESA)

except in the case of a

Table Indirect BMOV in which case the ESA has the
address of the Table Indirect entry and this register points
to the address of the BMOV instruction.

Registers: 0xD8–0xDA

SCSI Byte Count (SBC)
Read Only

SBC

SCSI Byte Count

[23:0]

This register contains the count of the number of bytes
transferred to or from the SCSI bus during any given
BMOV. This value is used in calculating the information
placed into the

Remaining Byte Count (RBC)

and

Updated Address (UA)

registers and should not need to

be used in normal operations.

There are several conditions for which the byte count
does not match the number of bytes transferred. If a
BMOV transfers an odd number of bytes across a wide
bus, the byte count at the end of the BMOV is one byte
greater than the number of bytes sent. This also occurs
in an odd byte count wide receive case. Lastly, when a
wide send occurs and a chain byte from a previous
transfer is present, the byte count does not reflect the
chain byte sent across the bus during that BMOV. To
determine the correct address to start fetching data from
after a phase mismatch, this byte is not counted for this
BMOV. It is included in the previous BMOV’s byte count.

SBC

This manual is related to the following products:

LSI53C1000