1 first dword, First dword, Load and store instruction – first dword – Avago Technologies LSI53C1000R User Manual
Page 281
Load and Store Instructions
5-39
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
5.7.1 First Dword
This section describes the first Dword of the Load and Store Instruction
register.
Figure 5.15 Load and Store Instruction – First Dword
IT[2:0]
Instruction Type
[31:29]
These bits should be 0b111, indicating the Load and
Store instruction.
DSA
DSA Relative
28
When this bit is cleared, the value in the
DMA SCRIPTS Pointer Save (DSPS)
is the actual 32-bit
memory address performs the Load/Store to/from. When
this bit is set, the chip determines the memory address to
perform the Load/Store to/from by adding the 24-bit signed
offset value in the
DMA SCRIPTS Pointer Save (DSPS)
to
the
.
R
Reserved
[27:26]
NF
No Flush (Store Instruction Only)
25
When this bit is set, the LSI53C1000R performs a Store
without flushing the prefetch unit. When this bit is cleared,
the Store instruction automatically flushes the prefetch
unit. Use No Flush if the source and destination are not
within four instructions of the current Store instruction.
This bit has no effect on the Load instruction.
Note:
This bit has no effect unless the Prefetch Enable bit in the
register is set. For information on
SCRIPTS instruction prefetching, refer to
Chapter 2, “Functional Description.”
LS
Load/Store
24
When this bit is set, the instruction is a Load. When
cleared, it is a Store.
31
29
28
27 26 25 24 23
16 15
3
2
0
DCMD Register
DBC Register
IT[2:0]
DSA
R
NF LS
A[7:0]
R
BC
1
1
1
x
0
0
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x