Avago Technologies LSI53C1000R - Manual (Page 104)

3-10 Signal Descriptions
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
3.4 SCSI Bus Interface Signals
Table 3.8 contains tables describing the SCSI Bus Interface Signal group.
The following tables describe the SCSI signals. Table 3.9 describes the
SCSI Signals and Table 3.10 describes the SCSI Control Signals.
Table 3.8 SCSI Bus Interface Signals
Name Bump Type Strength Description
SCLK F3 I N/A SCSI Clock derives all SCSI-related timings. The speed
of this clock must be 40 MHz. The clock frequency can be
quadrupled to create the 160 MHz clock required
internally for Ultra160 transfers.
Table 3.9 SCSI Signals
Name Bump Type Strength Description
SD[15:0]
−
Y1, AA2, AB2, AD1,
F2, G2, J4, H1, R4,
T5, T2, U2, U5, V2,
V4, W4 I/O SE:
48 mA
SCSI
LVD:
12 mA
UniLVD
SCSI Data.
LVD Mode: Negative half of LVDlink pair for
SCSI data. SD[15:0]
−
form the 16-bit SCSI
data bus.
SE Mode: SD[15:0]
−
form the 16-bit SCSI
data bus.
SD[15:0]+ W5, Y2, AA3, AC1,
D1, G1, H4, H2, P3,
R5, R2, T4, U4, U3,
V5, V3 I/O SE:
48 mA
SCSI
LVD:
12 mA
UniLVD
SCSI Data.
LVD Mode: Positive half of LVDlink pair for
SCSI data lines. SD[15:0]+ form the 16-bit
data bus.
SE Mode: SD[15:0]+ are at 0 V.
SDP[1:0]
−
W2, P4 I/O SE:
48 mA
SCSI
LVD:
12 mA
UniLVD
SCSI Parity.
LVD Mode: Negative half of LVDlink pair for
SCSI parity lines. SDP[1:0]
−
are the SCSI
data parity lines.
SE Mode: SDP[1:0]
−
are the SCSI data
parity lines.