Avago Technologies LSI53C1000R User Manual
Page 271
Transfer Control Instructions
5-29
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
When a Return instruction is executed, the value stored
in the
register is returned to the
register. The
LSI53C1000R does not check to see whether the Call
instruction has already been executed. It does not
generate an interrupt if a Return instruction is executed
without previously executing a Call instruction.
If the comparisons are false, the LSI53C1000R fetches
the next instruction from the address pointed to by the
register and the instruction
pointer is not modified.
Interrupt Instruction
The LSI53C1000R can do a true/false comparison of the
ALU carry bit, or compare the phase and/or data as
defined by the Phase Compare, Data Compare, and
True/False bit fields. If the comparisons are true, the
LSI53C1000R generates an interrupt by asserting the
INT/ signal.
The 32-bit address field stored in the
DMA SCRIPTS Pointer Save (DSPS)
register can contain
a unique interrupt service vector. When servicing the
interrupt, this unique status code allows the Interrupt
Service Routine to identify quickly the point at which the
interrupt occurred.
The LSI53C1000R halts and the
register must be written to
before starting any further operation.
Interrupt-on-the-Fly Instruction
The LSI53C1000R can do a true/false comparison of the
ALU carry bit or compare the phase and/or data as
defined by the Phase Compare, Data Compare, and
True/False bit fields. If the comparisons are true, and the
Interrupt-on-the-Fly bit
Interrupt Status Zero (ISTAT0),
bit 2) is set, the LSI53C1000R asserts the
Interrupt-on-the-Fly bit.
SCSIP[2:0]
SCSI Phase
[26:24]
This 3-bit field corresponds to the three SCSI bus phase
signals that are compared with the phase lines latched
when SREQ/ is asserted. Comparisons can be
performed to determine the SCSI phase actually being