Avago Technologies LSI53C1000R User Manual
Page 159
SCSI Registers
4-47
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
4.
If the SCSI Interrupt Pending bit is set, read the
SCSI Interrupt Status Zero (SIST0)
or
SCSI Interrupt Status One (SIST1)
register to
determine the cause of the SCSI Interrupt and return
to step 2.
5.
If the SCSI Interrupt Pending bit is cleared and the
DMA Interrupt Pending bit is set, write 0x00 to this
register.
6.
Read the
register to verify the
aborted interrupt and to determine if any other
interrupting conditions have occurred.
SRST
Software Reset
6
Setting this bit resets the LSI53C1000R. All operating
registers are cleared to their respective default values and
all SCSI signals are deasserted. Setting this bit does not
assert the SCSI RST/ signal. This reset does not clear the
ID Mode bit or any of the PCI configuration registers. This
bit is not self-clearing; it must be cleared to clear the reset
condition. A hardware reset also clears this bit.
Note:
If SCRIPTS are running, then the ABRT bit (bit 7) must be
set prior to setting the SRST bit.
SIGP
Signal Process
5
SIGP is a R/W bit that is writable at any time. It is polled
and reset using
. The SIGP bit
is used in various ways to pass a flag to or from a running
SCRIPTS instruction.
The only SCRIPTS instruction directly affected by the
SIGP bit is Wait For Selection/Reselection. Setting the
SIGP bit causes this instruction to jump to the alternate
address immediately. The instructions at the alternate
jump address should check the status of SIGP to
determine the cause of the jump. The SIGP bit is usable
at any time and is not restricted to the wait for
selection/reselection condition.
SEM
Semaphore
4
The SCRIPTS processor may set this bit using a
SCRIPTS register write instruction. An external processor
may also set it while the LSI53C1000R is executing a
SCRIPTS operation. This bit enables the LSI53C1000R